`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:52:45 08/31/2013 
// Design Name: 
// Module Name:    OnBoard7SegHexController 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module OnBoard7SegHexController(
	 input  clk,
	 input reset,
	 input enable,
	 input [3:0] address,
    input [31:0] dataIn,
	 output [31:0] dataOut,
	 input write,
	 output done,
	 output interrupt,
	 output [3:0] digitOnBus,
	 output [19:0] sevenSegs
    );
	 
	 parameter ON_BOARD_SEVEN_SEG_HEX_CONTROLLER_ID = 32'hA001003A;
	 
	 assign done = 1;
	 assign interrupt = 0;
	 
	 //controller stuff
	 
	 reg [3:0]digitOn;
	 assign digitOnBus = digitOn;
	 
	 reg [19:0] data;
	 assign sevenSegs = data;
	 always @(posedge clk , posedge reset) begin
		if(reset) {digitOn, data}<= {4'b0, 20'b0};
		else begin
			if(address == 4'd0 & write & enable) {digitOn, data} <= {dataIn[3:0], data};
			else if(address == 4'd1 & write & enable) begin
				digitOn <= digitOn;
				data[3:0] <= dataIn[20] ? dataIn[3:0] : data[3:0]; //setting digit 1
				data[7:4] <= dataIn[21] ? dataIn[7:4] : data[7:4]; //setting digit 2
				data[11:8] <= dataIn[22] ? dataIn[11:8] : data[11:8]; //setting digit 3
				data[15:12] <= dataIn[23] ? dataIn[15:12] : data[15:12]; //setting digit 4
				//COMMON TRAP: data[19:16] <= dataIn[23:20] ? dataIn[19:16] : data[19:16]; //setting dots
				data[19:16] <= (dataIn[23:20] & dataIn[19:16]) | (~dataIn[23:20] & data[19:16]); // setting dots
			end
			else {digitOn, data} <= {digitOn, data};
		end
	 end
	 
	 reg [31:0] dataOutReg;
	 assign dataOut = dataOutReg;
	 
	 always @(*) begin
		if(enable & ~write) begin
			case(address)
				4'h0: dataOutReg = {28'b0, digitOn};
				4'h1: dataOutReg = {12'b0, data};
				4'hF: dataOutReg = ON_BOARD_SEVEN_SEG_HEX_CONTROLLER_ID;
				default: dataOutReg = 32'b0;
			endcase
		end
		else dataOutReg = 32'b0;
	 end
endmodule